Field
This disclosure relates generally to data processing systems, and more specifically, to a configurable pipeline based on an error detection mode.
Related Art
Error correction code (ECC) and parity are commonly used to provide error detection and/or error correction for memories. Typically, ECC supports a higher level of error detection at a reduced performance as compared to using parity. Furthermore, certain users of a particular memory place a higher emphasis on error detection than others and are willing to sacrifice some performance to obtain a certain level of safety certification. Other users are not as stringent with respect to error detection and are therefore not willing to sacrifice performance for additional error detection capabilities. Furthermore, different error detection and/or error correction schemes affect execution timing within a processor instruction pipeline differently.